1. Field of the Invention
The present invention relates to a liquid crystal display, in more particular, to a circuit for driving the source lines of a liquid crystal display, which reduces the consumption power thereof.
2. Discussion of Related Art
A liquid crystal display (LCD) draws growing attentions as a display device for displaying video signals and studies and researches for this device are being actively carried out. In general, the LCD is roughly divided into a liquid crystal panel part and a driving part. The liquid crystal panel includes a lower glass plate on which pixel electrodes and thin film transistors (TFTs) are arranged in matrix form, a upper glass plate on which a common electrode and a color filter layer are formed, and a liquid crystal layer filled between the upper and the lower glass plates.
The driving part includes a video signal processor for processing video signals externally inputted, a controller for receiving a composite synchronous signal outputted from the video signal processor, dividing it into horizontal and vertical synchronous signals and controlling timing in response to mode (NTSC, PAL or SECAM) selecting signal, a source driver for supplying a signal voltage to the source lines of the liquid crystal panel in response to the output signal of the controller, and a gate driver for sequentially applying driving voltages to the scanning lines of the liquid crystal panel in response to the output signal of the controller. There have been actively performed researches for reducing the consumption power of the liquid crystal display constructed as above.
A conventional circuit and method for driving the source of a LCD is explained with reference to the attached drawings.
FIG. 1 shows the configuration of a conventional TFT-LCD. Referring to FIG. 1, the TFT-LCD includes a liquid crystal panel 10 having pixels each of which is located at each of points where a plurality of gate lines GL and a plurality of source lines SL intersect each other, a source driver 20 for providing each pixel with a video signal through the source lines SL, and a gate driver 30 for selecting a certain gate line GL of the liquid crystal panel 10 to turn on plural pixels. Here, each pixel consists of a TFT 1 whose gate is connected to the gate line GL and whose drain is connected to the source line SL, a storage capacitor Cs connected to the source of the TFT 1 in parallel, and a liquid crystal capacitor Clc.
FIG. 2 shows the configuration of the source driver of the conventional TFT-LCD. In this drawing, a 384-channel 6-bit driver is illustrated as an example of the source driver. That is, each of R, G, and B data is 6-bit and the number of the column lines is equal to 384. Referring to FIG. 2, the source driver includes a shift register 21, a sampling latch 22, a holding latch 23, a digital/analog converter 24, and an output buffer 25.
The shift register 21 shifts the horizontal synchronous signal pulse HSYNC in response to a source pulse clock HCLK, to output a latch enable clock to the sampling latch 22. The sampling latch 22 samples and latches digital R, G, and B data by column lines in response to the latch enable clock outputted from the shift register 21. The holding latch 23 simultaneously receives the R, G, and B data latched by the sampling latch 22 in response to a load signal LD to latch the R, G, and B data. The digital/analog converter 24 converts the digital R, G, and B data stored in the holding latch 23 into analog R, G, and B data. Then, the output buffer 25 amplifies signal current corresponding to the R, G, and B data to output it to the source line of the liquid crystal panel.
The source driver constructed as above samples and holds the digital R, G, and B data during one horizontal period, converts it into the analog R, G, and B data, and current-amplifies it. Here, when the holding latch 23 holds R, G, and B data corresponding to the nth column line, the sampling latch 22 samples R, G, and B data corresponding to the (n+1)th column line.
FIG. 3 shows the gate driver of the conventional TFT-LCD. Referring to FIG. 3, the gate driver includes a shift register 31, a level shifter, and an output buffer 33. The shift register 31 shifts the vertical synchronous signal pulse VSYNC in response to a gate pulse VCLK, to sequentially enable the scanning lines. The level shifter 32 sequentially level-shifts a signal applied to the scanning lines to output it to the output buffer 33. By doing so, the plural scanning lines connected to the output buffer 33 are sequentially enabled.
A method for driving the conventional TFT-LCD constructed as above is explained below.
First of all, the sampling latch 22 of the source driver 20 sequentially receives video data corresponding to a single pixel and stores video data corresponding to the source lines SL. The gate driver 30 outputs a gate line selection signal GLSS to select one of the plural gate lines GL. Then, the TFT 1 connected to the selected gate line GL is turned on so as to apply the video data stored in the holding latch 23 to the drain thereof, thereby displaying the video data on the liquid crystal panel 10.
Subsequently, the above-described operation is repeated to display video data on the liquid crystal panel 10.
At this time, the source driver 20 provides VCOM, positive and negative video signals to the liquid crystal panel 10 to display the video data thereon.
FIG. 4 shows the voltage range of the video signals of FIG. 1. Referring to FIG. 4, the positive and the negative video signals are alternately supplied to the pixels every time frame is changed, in order not to directly apply DC voltage to the liquid crystal during operation of the TFT-LCD and, for this, the electrode of the TFT-LCD upper plate is provided with the VCOM that is the medium voltage between the positive and negative video signals. In case where the positive and negative video signals are alternately applied to the pixels on the bases of the VCOM, however, light transmission curves of the liquid crystal do not agree with each other, generating flicker.
Accordingly, for the purpose of reducing the generation of flicker, four inversion modes are employed as shown in FIGS. 5A and 5B, 5C and 5D, 5E and 5F, and 5G and 5H respectively.
FIGS. 5A and 5B show the frame inversion mode in which the polarity of a video signal is modulated only when the frame is changed, and FIGS. 5C and 5D show the line inversion mode in which the video signal polarity varies every time the gate line GL is changed. Furthermore, FIGS. 5E and 5F show the column inversion mode in which the video signal polarity varies when the source line and the frame are changed, and FIGS. 5G and 5H show the dot inversion in which the polarity changes whenever each source line SL and gate line GL are changed and the frame is changed. The picture quality is good in the order of the frame inversion, line inversion, column inversion, and dot inversion, and the number of times of polarity change becomes larger in proportion to the picture quality, to result in the increases in power consumption. This is explained below in detail with reference to the dot inversion mode for driving the conventional LCD shown in FIG. 6. FIG. 6 shows the waveform of a video signal applied to odd-numbered source lines SL or even-numbered source lines SL of the liquid crystal panel 10. This illustrates that the polarity of the video signal of the source lines SL is modulated at every gate line change on the basis of the VCOM.
Here, it is assumed that the entire TFT-LCD panel displays the same gray color, the variation width (V) of the video signal of the source lines SL becomes twice that of the VCOM plus positive video signal or that of the VCOM plus negative video signal. Accordingly, the conventional dot inversion consumes a large amount of power because the polarity of the video signal changes from positive to negative or from negative to positive on the basis of the VCOM at every time when the gate line GL is changed.
FIG. 6 shows the video signal swing width when a black image is displayed using the normally-white mode liquid crystal. In this case, every horizontal period requires a voltage swing with a wide width, this voltage swing being obtained by energy provided by the voltage power VDD of the output amplifier, and power consumption occurs at every two horizontal periods (period: H).
FIG. 7 is a circuit diagram of a general CMOS for driving a capacitance load. Referring to FIG. 7, the source of a PMOS transistor P1 is connected to a power supply VH and its drain is connected to the drain of an NMOS transistor N1 to construct an output side, the source of the NMOS transistor N1 is connected to other power supply VL, the gates of the NMOS and the PMOS transistors N1 and P1 receive an output signal (or input signal) frequency F, and a load capacitor CLOAD is connected between the drains of the NMOS and the PMOS transistors N1 and P1 and the source of the NMOS transistor N1.
The consumption power of the conventional CMOS driving circuit constructed as above is represented by the following equation (1).
PCCNV=CLOADxc2x7VHxc2x7(VHxe2x88x92VL)xc2x7Fxe2x80x83xe2x80x83(1)
where CLOAD indicates the capacitance of the load capacitor CLOAD, and F indicates the output signal (or input signal) frequency, and VH greater than VL.
However, in the conventional method of driving the source of the LCD, a large amount of power consumption occurs at every two horizontal periods because the amount of power consumed for driving the source is proportional to the swing width of the video signal, requiring a large amount of consumption power.
Accordingly, the present invention is directed to a circuit for driving the source lines of a liquid crystal display that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a circuit for driving the source lines of a liquid crystal display, which reduces consumption power required for polarity conversion accompanying a voltage swing with a wide width and, at the same time, decreases the driving consumption power of an amplifier.
To accomplish the object of the present invention, there is provided a source driving circuit of a liquid crystal display, the source driving circuit having a shift register, a sampling latch, a holding latch, a digital/analog converter and an output buffer, the source driving circuit comprising: a first polarity modulator for performing polarity modulation of odd-numbered source lines; a second polarity modulator for performing polarity modulation of even-numbered source lines, opposite to the first polarity modulator; and a plurality of multiplexers or switches for selecting one of the output of the output buffer and the outputs of the first and the second polarity modulators in response to an external control signal, to output the selected one to pixels.
For the source driving circuit of a liquid crystal display of this invention, there is also provided a source driving method in a liquid crystal display, which applies negative and positive video signals to source lines of the liquid crystal display including a first and a second plates and a liquid crystal being inserted therebetween, in which each video signal is applied, with its voltage being divided two phases of polarity modulation and gray scale decision.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.